mem parses today (MemStmt) but has zero representation from HIR
onward — no HIR item, no strata-check handling, no arch-IR node, no
CIRCT lowering. This blocks any array-backed storage past hand-inlined
depth-4 designs, so the model needs deciding before implementation
starts rather than discovered mid-PR.

Core decision: mem is a storage-class declarator over the existing
TypeKind::Array (no new Type variant needed), reads are registered
(1-cycle) not combinational since real BRAM is synchronous and
reg [T; N] already covers combinational-read storage, v0 is one read
port + one write port concurrently usable (forced by fifo.strata's
same-cycle push/pop), and indexing accepts any Index<N>-typed value
(constant or runtime) since Index<N> already proves boundedness by
construction — no separate bounds-check pass needed.

Flags honestly that fifo.strata/cdc_bridge.strata assume same-cycle
combinational reads today and will need a one-cycle rework once mem
timing is actually enforced — expected fallout, not a regression,
since nothing enforces the assumption currently. CIRCT lowering target
(seq dialect memory ops vs. register-array-plus-mux fallback) is
flagged as a research spike against the pinned firtool version before
implementation, not assumed.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>