# Cleaned up RISC-V instruction creation, added 32-bit immediates \(\#6077\) · gitcafe/zig

[View on GitCafe](https://git.cafe/gitcafe/zig/commit/fa8935426b425110a89c6a2008013c500b7a3a79)

Repository: [gitcafe/zig](https://git.cafe/gitcafe/zig)

Visibility: public

Requested revision: fa8935426b425110a89c6a2008013c500b7a3a79

Requested commit: fa8935426b425110a89c6a2008013c500b7a3a79

Commit: fa8935426b425110a89c6a2008013c500b7a3a79

Tree: c36c70a2a595b33e2b393e523fdbe4aae7a80b22

Author: Eleanor Bartle

Committer: GitHub

## Message

```
Cleaned up RISC-V instruction creation, added 32-bit immediates (#6077)

* Implemented all R-type arithmetic/logical instructions

* Implemented all I-type arithmetic/logical instructions

* Implemented all load and store instructions

* Implemented all of RV64I except FENCE

```

## Parents

- [3cc1f8b62477c37c938863cba0ec0409e4c9c0be](https://git.cafe/gitcafe/zig/commit/3cc1f8b62477c37c938863cba0ec0409e4c9c0be?format=markdown)

[Source at this commit](https://git.cafe/gitcafe/zig/tree/fa8935426b425110a89c6a2008013c500b7a3a79?format=markdown)