# stage2 ARM: generate correct variants of ldr instruction · gitcafe/zig

[View on GitCafe](https://git.cafe/gitcafe/zig/commit/f48f4baf676061742adb9674bc5e43e82c63f96a)

Repository: [gitcafe/zig](https://git.cafe/gitcafe/zig)

Visibility: public

Requested revision: f48f4baf676061742adb9674bc5e43e82c63f96a

Requested commit: f48f4baf676061742adb9674bc5e43e82c63f96a

Commit: f48f4baf676061742adb9674bc5e43e82c63f96a

Tree: 046a8c7ce6342b6bb929f0b5655efcfcddc66a4f

Author: joachimschmidt557

Committer: joachimschmidt557

## Message

```
stage2 ARM: generate correct variants of ldr instruction

When loading an i16 for example, generate ldrsh instead of ldrh

```

## Parents

- [8ef80cfaab2a74506d7b3a866dc066d9cd281f55](https://git.cafe/gitcafe/zig/commit/8ef80cfaab2a74506d7b3a866dc066d9cd281f55?format=markdown)

[Source at this commit](https://git.cafe/gitcafe/zig/tree/f48f4baf676061742adb9674bc5e43e82c63f96a?format=markdown)