# stage2: add support for loops in LLVM backend · gitcafe/zig

[View on GitCafe](https://git.cafe/gitcafe/zig/commit/e1d8073d2fc0df6fbc5ce983312e3da374a9889b)

Repository: [gitcafe/zig](https://git.cafe/gitcafe/zig)

Visibility: public

Requested revision: e1d8073d2fc0df6fbc5ce983312e3da374a9889b

Requested commit: e1d8073d2fc0df6fbc5ce983312e3da374a9889b

Commit: e1d8073d2fc0df6fbc5ce983312e3da374a9889b

Tree: 11d8c5aa24c3c09dfec529c2d9f150511623c7b9

Author: Timon Kruiper

Committer: Andrew Kelley

## Message

````
stage2: add support for loops in LLVM backend

A simple `while(true) {}` loop generates the following LLVMIR:
```
define i32 @main() {
Entry:
  br label %Loop

Loop:                                 ; preds = %Loop, %Entry
  br label %Loop
}
```

Also implement TZIR printing for loops and add a corresponding test.

````

## Parents

- [2117489e05ddf7cc4653feecbf47b3637276d6b6](https://git.cafe/gitcafe/zig/commit/2117489e05ddf7cc4653feecbf47b3637276d6b6?format=markdown)

[Source at this commit](https://git.cafe/gitcafe/zig/tree/e1d8073d2fc0df6fbc5ce983312e3da374a9889b?format=markdown)