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Code
stage2: use lowerToRmEnc to lower two-operand imul
Fix mismatched register sizes in codegen.
dba5df64ea
Jakub Konka committed on 12/23/2021, 7:51:48 PM
parent
c50bb2b
Files Changed
2 files changed
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Ignore whitespace
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src/arch/x86_64
src/arch/x86_64
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CodeGen.zig
CodeGen.zig
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Emit.zig
Emit.zig
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