# SIMD size suggestions: suggestions code now compiles, added more · gitcafe/zig

[View on GitCafe](https://git.cafe/gitcafe/zig/commit/d1d892c83ca7beaf235147341b7e68d3619dd829)

Repository: [gitcafe/zig](https://git.cafe/gitcafe/zig)

Visibility: public

Requested revision: d1d892c83ca7beaf235147341b7e68d3619dd829

Requested commit: d1d892c83ca7beaf235147341b7e68d3619dd829

Commit: d1d892c83ca7beaf235147341b7e68d3619dd829

Tree: 8b920ee96faff0954d7c29da8144bc9fa906a36e

Author: Dan Ellis Echavarria

Committer: Veikka Tuominen

## Message

```
SIMD size suggestions: suggestions code now compiles, added more
architectures
The idea behind this is using the register capabilities in safe amounts,
 there is still some consideration to be done.
+ Fixed compile error using std.Target.<arch>.featureSetHas
+ X86 MMX and "3DNOW" 64 bits register usage considered for vector size
+ Added ARM Neon recommened usage of 128 bits (The size of the register)
+ Added AARCH64 Neon and SVE for 128 bits. SVE could use in theory up to
  2048 bits, but found only evidence of functional 512 bits on a super
       computer, decided on using 128 bits as a safety
+ Added Altivec recommendation of using the 128 bits long register
+ Using MIPS msa 2x64bits capabilities, usage of 64 bits registers for MDMX
  systems, need testing on how using bigger values affect performance
+ Using V extension on RISC-V, which is extendable via instructions, decided on 128 bits
  as a value to not use all registers
+ in SPARC the 64 bits registers are used, a max of 32 registers
  are to be used for configurable simd instructions, decided on using
the size of the register, need testing on performance hit on using a
bigger sized register vector size

```

## Parents

- [8e75ba653b03477229cf72211e8a8bfe7b071254](https://git.cafe/gitcafe/zig/commit/8e75ba653b03477229cf72211e8a8bfe7b071254?format=markdown)

[Source at this commit](https://git.cafe/gitcafe/zig/tree/d1d892c83ca7beaf235147341b7e68d3619dd829?format=markdown)