# stage2: LLVM backend: properly set module target data · gitcafe/zig

[View on GitCafe](https://git.cafe/gitcafe/zig/commit/bdbedff910e18e18dc31db84a80607435e9b6ee0)

Repository: [gitcafe/zig](https://git.cafe/gitcafe/zig)

Visibility: public

Requested revision: bdbedff910e18e18dc31db84a80607435e9b6ee0

Requested commit: bdbedff910e18e18dc31db84a80607435e9b6ee0

Commit: bdbedff910e18e18dc31db84a80607435e9b6ee0

Tree: d0081d6089f09f797662b6f22d05a73895e5aacd

Author: Andrew Kelley

Committer: Andrew Kelley

## Message

```
stage2: LLVM backend: properly set module target data

Also fix tripping LLVM assert having to do with 0 bit integers.
stage2 behavior tests now run clean in a debug build of llvm 12.

```

## Parents

- [ea6706b6f406606a7523e35e34e390fb880b607e](https://git.cafe/gitcafe/zig/commit/ea6706b6f406606a7523e35e34e390fb880b607e?format=markdown)

[Source at this commit](https://git.cafe/gitcafe/zig/tree/bdbedff910e18e18dc31db84a80607435e9b6ee0?format=markdown)