# stage2: Implement setReg, call, ret, asm for ARM · gitcafe/zig

[View on GitCafe](https://git.cafe/gitcafe/zig/commit/b2254023e464027abfcbff809e991ff22cf581e0)

Repository: [gitcafe/zig](https://git.cafe/gitcafe/zig)

Visibility: public

Requested revision: b2254023e464027abfcbff809e991ff22cf581e0

Requested commit: b2254023e464027abfcbff809e991ff22cf581e0

Commit: b2254023e464027abfcbff809e991ff22cf581e0

Tree: c02ebe998078bc8f4a6729dcc491e7f6f8462628

Author: joachimschmidt557

Committer: joachimschmidt557

## Message

```
stage2: Implement setReg, call, ret, asm for ARM

These changes enable a Hello World example. However, all implemented
codegen is not yet feature-complete.

- asm only supports 'svc #0' at the moment
- call only supports leaf functions at the moment
- setReg uses a naive method at the moment

```

## Parents

- [1c53c070535c519cbdc39a2094a24723f5245799](https://git.cafe/gitcafe/zig/commit/1c53c070535c519cbdc39a2094a24723f5245799?format=markdown)

[Source at this commit](https://git.cafe/gitcafe/zig/tree/b2254023e464027abfcbff809e991ff22cf581e0?format=markdown)