```zig
export fn entry() void {
    var c: i32 = 1234;
    var x = switch (c) {
        1 => u8(1),
        2...4 => u16(2),
        else => u32(3),
    };
}
```

```llvm
define void @entry() #2 !dbg !35 {
Entry:
  %c = alloca i32, align 4
  %x = alloca i32, align 4
  store i32 1234, i32* %c, align 4, !dbg !44
  call void @llvm.dbg.declare(metadata i32* %c, metadata !39, metadata !DIExpression()), !dbg !44
  %0 = load i32, i32* %c, align 4, !dbg !45
  %1 = icmp sge i32 %0, 2, !dbg !46
  %2 = icmp sle i32 %0, 4, !dbg !46
  %3 = and i1 %1, %2, !dbg !46
  br i1 %3, label %SwitchRangeYes, label %SwitchRangeNo, !dbg !46

SwitchRangeYes:                                   ; preds = %Entry
  br label %SwitchEnd, !dbg !45

SwitchElse:                                       ; preds = %SwitchRangeNo
  br label %SwitchEnd, !dbg !45

SwitchProng:                                      ; preds = %SwitchRangeNo
  br label %SwitchEnd, !dbg !45

SwitchEnd:                                        ; preds = %SwitchProng, %SwitchElse, %SwitchRangeYes
  %4 = phi i32 [ 2, %SwitchRangeYes ], [ 3, %SwitchElse ], [ 1, %SwitchProng ], !dbg !45
  store i32 %4, i32* %x, align 4, !dbg !45
  call void @llvm.dbg.declare(metadata i32* %x, metadata !42, metadata !DIExpression()), !dbg !47
  ret void, !dbg !48

SwitchRangeNo:                                    ; preds = %Entry
  switch i32 %0, label %SwitchElse [
    i32 1, label %SwitchProng
  ], !dbg !45
}
```