# stage2: add inline memset for x86_64 backend · gitcafe/zig

[View on GitCafe](https://git.cafe/gitcafe/zig/commit/aaa641feba8866ac38f2d06a8db2a24fa134e2f5)

Repository: [gitcafe/zig](https://git.cafe/gitcafe/zig)

Visibility: public

Requested revision: aaa641feba8866ac38f2d06a8db2a24fa134e2f5

Requested commit: aaa641feba8866ac38f2d06a8db2a24fa134e2f5

Commit: aaa641feba8866ac38f2d06a8db2a24fa134e2f5

Tree: 3b528f866b44275ea4762d224bdfc6263c3fd273

Author: Jakub Konka

Committer: Jakub Konka

## Message

```
stage2: add inline memset for x86_64 backend

* introduce new Mir tag `mov_mem_index_imm` which selects instruction
  of the form `OP ptr [reg + rax*1 + imm32], imm32` where the encoded
  flags select the appropriate ptr width for memory store operation
  (note that scale is fixed and set at 1)

```

## Parents

- [4938fb8f5ca9551b69036fdb644103ffc9ef49cf](https://git.cafe/gitcafe/zig/commit/4938fb8f5ca9551b69036fdb644103ffc9ef49cf?format=markdown)

[Source at this commit](https://git.cafe/gitcafe/zig/tree/aaa641feba8866ac38f2d06a8db2a24fa134e2f5?format=markdown)