# update RISC-V target CPU features · gitcafe/zig

[View on GitCafe](https://git.cafe/gitcafe/zig/commit/a9f19221e99d9470d936f63ecfa20c735e175a2c)

Repository: [gitcafe/zig](https://git.cafe/gitcafe/zig)

Visibility: public

Requested revision: a9f19221e99d9470d936f63ecfa20c735e175a2c

Requested commit: a9f19221e99d9470d936f63ecfa20c735e175a2c

Commit: a9f19221e99d9470d936f63ecfa20c735e175a2c

Tree: a4fbff925d0cef1cce369b4e78b01690504f2e0e

Author: Andrew Kelley

Committer: Andrew Kelley

## Message

```
update RISC-V target CPU features

```

## Parents

- [50a5fc98dc7d458cb731980d1231ee6e1a7eb880](https://git.cafe/gitcafe/zig/commit/50a5fc98dc7d458cb731980d1231ee6e1a7eb880?format=markdown)

[Source at this commit](https://git.cafe/gitcafe/zig/tree/a9f19221e99d9470d936f63ecfa20c735e175a2c?format=markdown)