# basic riscv support · gitcafe/zig

[View on GitCafe](https://git.cafe/gitcafe/zig/commit/a3854d042e0d05a87ae9f0b71d12474c8d0e57ec)

Repository: [gitcafe/zig](https://git.cafe/gitcafe/zig)

Visibility: public

Requested revision: a3854d042e0d05a87ae9f0b71d12474c8d0e57ec

Requested commit: a3854d042e0d05a87ae9f0b71d12474c8d0e57ec

Commit: a3854d042e0d05a87ae9f0b71d12474c8d0e57ec

Tree: 7f0a97f024aea3eb3d1f6775acd9439075aebe0f

Author: Andrew Kelley

Committer: Andrew Kelley

## Message

```
basic riscv support

llvm is giving me `error: couldn't allocate output register for
constraint '{a0}'` which is a bug that needs to be fixed upstream.

```

## Parents

- [07f0de6a8a9a152cfbd76e458d99d992b59e9e06](https://git.cafe/gitcafe/zig/commit/07f0de6a8a9a152cfbd76e458d99d992b59e9e06?format=markdown)

[Source at this commit](https://git.cafe/gitcafe/zig/tree/a3854d042e0d05a87ae9f0b71d12474c8d0e57ec?format=markdown)