# stage2 sparcv9: Add register definitions & instruction formats · gitcafe/zig

[View on GitCafe](https://git.cafe/gitcafe/zig/commit/a212d5931d99653de28933499a2a0bded1b8d2db)

Repository: [gitcafe/zig](https://git.cafe/gitcafe/zig)

Visibility: public

Requested revision: a212d5931d99653de28933499a2a0bded1b8d2db

Requested commit: a212d5931d99653de28933499a2a0bded1b8d2db

Commit: a212d5931d99653de28933499a2a0bded1b8d2db

Tree: 60963a4b9cd8e68c2cdd3489f5ca701bb69df141

Author: Koakuma

Committer: Koakuma

## Message

```
stage2 sparcv9: Add register definitions & instruction formats

This adds the GPR/FPR register definitions and instruction formats
for SPARCv9.
I need to implement a separate enc() function because the register
values for the FPRs have to be encoded to a special format that's
separate from the normal register ID.

```

## Parents

- [8a43d67c3bf878fa32ef4876897a32969a4b5d24](https://git.cafe/gitcafe/zig/commit/8a43d67c3bf878fa32ef4876897a32969a4b5d24?format=markdown)

[Source at this commit](https://git.cafe/gitcafe/zig/tree/a212d5931d99653de28933499a2a0bded1b8d2db?format=markdown)