# stage2 RISCV64: implement add, sub for registers · gitcafe/zig

[View on GitCafe](https://git.cafe/gitcafe/zig/commit/a153732d5a86f7d8c5ca5bc91cfad1ccf0f8f573)

Repository: [gitcafe/zig](https://git.cafe/gitcafe/zig)

Visibility: public

Requested revision: a153732d5a86f7d8c5ca5bc91cfad1ccf0f8f573

Requested commit: a153732d5a86f7d8c5ca5bc91cfad1ccf0f8f573

Commit: a153732d5a86f7d8c5ca5bc91cfad1ccf0f8f573

Tree: 97f065f4df0b8b6f94ed3a2dc2ebed01152757af

Author: joachimschmidt557

Committer: joachimschmidt557

## Message

```
stage2 RISCV64: implement add, sub for registers

```

## Parents

- [7cdc47a4e08cd32e1f68ca4aad3ca22b11e4e7b2](https://git.cafe/gitcafe/zig/commit/7cdc47a4e08cd32e1f68ca4aad3ca22b11e4e7b2?format=markdown)

[Source at this commit](https://git.cafe/gitcafe/zig/tree/a153732d5a86f7d8c5ca5bc91cfad1ccf0f8f573?format=markdown)