# riscv: implement 64 bit immediate into register loading · gitcafe/zig

[View on GitCafe](https://git.cafe/gitcafe/zig/commit/9b2a4582c983a4171de9ab9843d0af1d807ddbff)

Repository: [gitcafe/zig](https://git.cafe/gitcafe/zig)

Visibility: public

Requested revision: 9b2a4582c983a4171de9ab9843d0af1d807ddbff

Requested commit: 9b2a4582c983a4171de9ab9843d0af1d807ddbff

Commit: 9b2a4582c983a4171de9ab9843d0af1d807ddbff

Tree: d48479067b383ab4e7ef1ff30d53eca7e3e33e8a

Author: David Rubin

Committer: David Rubin

## Message

```
riscv: implement 64 bit immediate into register loading

LLVM has a better myriad sequence for this, where they don't allocate
a temporary register, but for now this will do.

```

## Parents

- [f67fa73fe8bc5cc38af826c396d912b7f72b3261](https://git.cafe/gitcafe/zig/commit/f67fa73fe8bc5cc38af826c396d912b7f72b3261?format=markdown)

[Source at this commit](https://git.cafe/gitcafe/zig/tree/9b2a4582c983a4171de9ab9843d0af1d807ddbff?format=markdown)