# fix RISC-V assembly CPU features · gitcafe/zig

[View on GitCafe](https://git.cafe/gitcafe/zig/commit/90c73d8768bd51c84a5bf3d589d31abce6d93d37)

Repository: [gitcafe/zig](https://git.cafe/gitcafe/zig)

Visibility: public

Requested revision: 90c73d8768bd51c84a5bf3d589d31abce6d93d37

Requested commit: 90c73d8768bd51c84a5bf3d589d31abce6d93d37

Commit: 90c73d8768bd51c84a5bf3d589d31abce6d93d37

Tree: 3a8cd89a878209178a2c8561d15ef33cb6fb118e

Author: Andrew Kelley

Committer: Andrew Kelley

## Message

```
fix RISC-V assembly CPU features

Previously, Zig did not properly communicate the target CPU features for
RISC-V to clang assembler, because Clang has a different way to pass CPU
features for C code and for assembly code. This commit makes Zig pass a
RISC-V -march flag in order to communicate CPU features to Clang when
compiling assembly files.

```

## Parents

- [515d6430c0298daf304e48b46e6b43802bbfdab4](https://git.cafe/gitcafe/zig/commit/515d6430c0298daf304e48b46e6b43802bbfdab4?format=markdown)

[Source at this commit](https://git.cafe/gitcafe/zig/tree/90c73d8768bd51c84a5bf3d589d31abce6d93d37?format=markdown)