# update the CPU target features and models · gitcafe/zig

[View on GitCafe](https://git.cafe/gitcafe/zig/commit/8f1408578cb255fbbdc555d746b25cefb331105e)

Repository: [gitcafe/zig](https://git.cafe/gitcafe/zig)

Visibility: public

Requested revision: 8f1408578cb255fbbdc555d746b25cefb331105e

Requested commit: 8f1408578cb255fbbdc555d746b25cefb331105e

Commit: 8f1408578cb255fbbdc555d746b25cefb331105e

Tree: e11a39bf04e1627ee5db084e82f64a05220a9a56

Author: Andrew Kelley

Committer: Andrew Kelley

## Message

```
update the CPU target features and models

Rather than directly pasting the output from the
target-details-generator tool, we have to look at the diff line by line
and decide how to incorporate the changes.

The baseline abstraction is something that Zig provides.

The changes to x86 appear to be incorrect. After LLVM commit
3ad09fd03c51823aeb0bcbd7898aada33e9228d6 the CPU features are stored in
a different data layout in their tables, and so we need to update the
target details extraction tool to match.

```

## Parents

- [bbb3403b5dff854b01989882a539b29a9e33d732](https://git.cafe/gitcafe/zig/commit/bbb3403b5dff854b01989882a539b29a9e33d732?format=markdown)

[Source at this commit](https://git.cafe/gitcafe/zig/tree/8f1408578cb255fbbdc555d746b25cefb331105e?format=markdown)