# fix RISC-V assembly CPU features · gitcafe/zig

[View on GitCafe](https://git.cafe/gitcafe/zig/commit/8be29674a95b8a6dd52b439701180e9e74e221aa)

Repository: [gitcafe/zig](https://git.cafe/gitcafe/zig)

Visibility: public

Requested revision: 8be29674a95b8a6dd52b439701180e9e74e221aa

Requested commit: 8be29674a95b8a6dd52b439701180e9e74e221aa

Commit: 8be29674a95b8a6dd52b439701180e9e74e221aa

Tree: 4056c802918a9d8cd38418545ac539b11ad8bd24

Author: Andrew Kelley

Committer: Andrew Kelley

## Message

```
fix RISC-V assembly CPU features

Previously, Zig did not properly communicate the target CPU features for
RISC-V to clang assembler, because Clang has a different way to pass CPU
features for C code and for assembly code. This commit makes Zig pass a
RISC-V -march flag in order to communicate CPU features to Clang when
compiling assembly files.

```

## Parents

- [52ead255a27e62e7c33748b04971aca49e06b5d8](https://git.cafe/gitcafe/zig/commit/52ead255a27e62e7c33748b04971aca49e06b5d8?format=markdown)

[Source at this commit](https://git.cafe/gitcafe/zig/tree/8be29674a95b8a6dd52b439701180e9e74e221aa?format=markdown)