fix RISC-V assembly CPU features

Previously, Zig did not properly communicate the target CPU features for
RISC-V to clang assembler, because Clang has a different way to pass CPU
features for C code and for assembly code. This commit makes Zig pass a
RISC-V -march flag in order to communicate CPU features to Clang when
compiling assembly files.
8be29674a9Andrew Kelley committed on 6/18/2021, 3:28:37 AMparent52ead25
1 file changedLine totals unavailable