# std.Target: Fix Cpu.Model.generic\(\) for arc, csky, and xtensa\. · gitcafe/zig

[View on GitCafe](https://git.cafe/gitcafe/zig/commit/7d71e794dd22e4c2a38d3aafd4fc604b36d2ac5e)

Repository: [gitcafe/zig](https://git.cafe/gitcafe/zig)

Visibility: public

Requested revision: 7d71e794dd22e4c2a38d3aafd4fc604b36d2ac5e

Requested commit: 7d71e794dd22e4c2a38d3aafd4fc604b36d2ac5e

Commit: 7d71e794dd22e4c2a38d3aafd4fc604b36d2ac5e

Tree: 1124c1b92e5828ca1d7fddb65233f422717b613b

Author: Alex Rønne Petersen

Committer: Alex Rønne Petersen

## Message

```
std.Target: Fix Cpu.Model.generic() for arc, csky, and xtensa.

Only targets for which we don't source CPU models/features from LLVM should use
the fallback prong in this switch. Also make it exhaustive to catch similar
mistakes in the future.

```

## Parents

- [cb1ac0bb2fb95424118404160704d53a3ff2a2c0](https://git.cafe/gitcafe/zig/commit/cb1ac0bb2fb95424118404160704d53a3ff2a2c0?format=markdown)

[Source at this commit](https://git.cafe/gitcafe/zig/tree/7d71e794dd22e4c2a38d3aafd4fc604b36d2ac5e?format=markdown)