# stage2 ARM: add lsl, lsr, asr, ror psuedo-instructions · gitcafe/zig

[View on GitCafe](https://git.cafe/gitcafe/zig/commit/7aecf90d2eeead6796569713635f523cbe17295e)

Repository: [gitcafe/zig](https://git.cafe/gitcafe/zig)

Visibility: public

Requested revision: 7aecf90d2eeead6796569713635f523cbe17295e

Requested commit: 7aecf90d2eeead6796569713635f523cbe17295e

Commit: 7aecf90d2eeead6796569713635f523cbe17295e

Tree: 1259d94657f8e477da3cead3a5da05f33c130308

Author: joachimschmidt557

Committer: joachimschmidt557

## Message

```
stage2 ARM: add lsl, lsr, asr, ror psuedo-instructions

```

## Parents

- [2f6dbaa0ea7307dd6806082b07266a43db5da950](https://git.cafe/gitcafe/zig/commit/2f6dbaa0ea7307dd6806082b07266a43db5da950?format=markdown)

[Source at this commit](https://git.cafe/gitcafe/zig/tree/7aecf90d2eeead6796569713635f523cbe17295e?format=markdown)