# stage2 ARM: make Mir.Inst.cond = \.al default · gitcafe/zig

[View on GitCafe](https://git.cafe/gitcafe/zig/commit/77ca77cf144e3f7e8be53b6e4220a4efc313628b)

Repository: [gitcafe/zig](https://git.cafe/gitcafe/zig)

Visibility: public

Requested revision: 77ca77cf144e3f7e8be53b6e4220a4efc313628b

Requested commit: 77ca77cf144e3f7e8be53b6e4220a4efc313628b

Commit: 77ca77cf144e3f7e8be53b6e4220a4efc313628b

Tree: f7c23b14aa8f503f9358e4e312b9727b8c512e18

Author: joachimschmidt557

Committer: joachimschmidt557

## Message

```
stage2 ARM: make Mir.Inst.cond = .al default

```

## Parents

- [d66c97d0ef0434ce0814d1921877b9ffa877a645](https://git.cafe/gitcafe/zig/commit/d66c97d0ef0434ce0814d1921877b9ffa877a645?format=markdown)

[Source at this commit](https://git.cafe/gitcafe/zig/tree/77ca77cf144e3f7e8be53b6e4220a4efc313628b?format=markdown)