# AstGen: fix latent bug causing incorrect elision of \`dbg_stmt\` instructions · gitcafe/zig

[View on GitCafe](https://git.cafe/gitcafe/zig/commit/6a87e42c2ea070a6273317bbb005029d95ceae49)

Repository: [gitcafe/zig](https://git.cafe/gitcafe/zig)

Visibility: public

Requested revision: 6a87e42c2ea070a6273317bbb005029d95ceae49

Requested commit: 6a87e42c2ea070a6273317bbb005029d95ceae49

Commit: 6a87e42c2ea070a6273317bbb005029d95ceae49

Tree: 2b484cdc2b5f8d25a81e67f6bb8df8f0d2b0600a

Author: mlugg

Committer: mlugg

## Message

```
AstGen: fix latent bug causing incorrect elision of `dbg_stmt` instructions

Thanks to jacobly0 for figuring this out. The chain of events causing
the failure this triggered is as follows.

* As of a recent commit, certain bodies no longer emit a redundant
  `block`, meaning there are more likely to be "interesting"
  instructions (i.e. not blocks) at the end of parent GenZir scopes.

* When emitting the first `dbg_stmt` in such a body, the elision logic
  incorrectly looks at a tag from an instruction in an enclosing scope.

* The tag of this instruction may be `undefined`, meaning that in unsafe
  builds it may be incorrectly identified as a `dbg_stmt` instruction.

* This instruction from another body is clobbered rather than emitting
  an actual `dbg_stmt` instruction. Note that this does not produce
  invalid ZIR, since the creator of the undefined instruction replaces
  the previously-undefined payload later.

```

## Parents

- [36d0afbf2871ddaa6717807ae0050cb06cb2cd0d](https://git.cafe/gitcafe/zig/commit/36d0afbf2871ddaa6717807ae0050cb06cb2cd0d?format=markdown)

[Source at this commit](https://git.cafe/gitcafe/zig/tree/6a87e42c2ea070a6273317bbb005029d95ceae49?format=markdown)