# stage2: guidance on how to implement switch expressions · gitcafe/zig

[View on GitCafe](https://git.cafe/gitcafe/zig/commit/623d5f442c832ec0ea2a07aba73b8e2eae57191c)

Repository: [gitcafe/zig](https://git.cafe/gitcafe/zig)

Visibility: public

Requested revision: 623d5f442c832ec0ea2a07aba73b8e2eae57191c

Requested commit: 623d5f442c832ec0ea2a07aba73b8e2eae57191c

Commit: 623d5f442c832ec0ea2a07aba73b8e2eae57191c

Tree: bea996aaf34c60b2be183754415905ee1c77c2f4

Author: Andrew Kelley

Committer: Andrew Kelley

## Message

````
stage2: guidance on how to implement switch expressions

Here's what I think the ZIR should be. AstGen is not yet implemented to
match this, and the main implementation of analyzeSwitch in Sema is not
yet implemented to match it either.

Here are some example byte size reductions from master branch, with the
ZIR memory layout from this commit:

```
switch (foo) {
  a => 1,
  b => 2,
  c => 3,
  d => 4,
}
```

184 bytes (master) => 40 bytes (this branch)

```
switch (foo) {
  a, b => 1,
  c..d, e, f => 2,
  g => 3,
  else => 4,
}
```

240 bytes (master) => 80 bytes (this branch)

````

## Parents

- [281a7baaeac6b6b3c8c78124f5e484f7ee101cf0](https://git.cafe/gitcafe/zig/commit/281a7baaeac6b6b3c8c78124f5e484f7ee101cf0?format=markdown)

[Source at this commit](https://git.cafe/gitcafe/zig/tree/623d5f442c832ec0ea2a07aba73b8e2eae57191c?format=markdown)