Here's what I think the ZIR should be. AstGen is not yet implemented to
match this, and the main implementation of analyzeSwitch in Sema is not
yet implemented to match it either.

Here are some example byte size reductions from master branch, with the
ZIR memory layout from this commit:

```
switch (foo) {
  a => 1,
  b => 2,
  c => 3,
  d => 4,
}
```

184 bytes (master) => 40 bytes (this branch)

```
switch (foo) {
  a, b => 1,
  c..d, e, f => 2,
  g => 3,
  else => 4,
}
```

240 bytes (master) => 80 bytes (this branch)