# riscv: reorganize \`binOp\` and implement \`cmp_imm_gte\` MIR · gitcafe/zig

[View on GitCafe](https://git.cafe/gitcafe/zig/commit/5e010b6deac7ad34f0cd06d507fc468fd98f9abc)

Repository: [gitcafe/zig](https://git.cafe/gitcafe/zig)

Visibility: public

Requested revision: 5e010b6deac7ad34f0cd06d507fc468fd98f9abc

Requested commit: 5e010b6deac7ad34f0cd06d507fc468fd98f9abc

Commit: 5e010b6deac7ad34f0cd06d507fc468fd98f9abc

Tree: d331bfc3ab68221d9e8f569d8b30f0e3374491d5

Author: David Rubin

Committer: David Rubin

## Message

```
riscv: reorganize `binOp` and implement `cmp_imm_gte` MIR

this was an annoying one to do, as there is no (to my knowledge) myriad sequence
that will allow us to do `gte` compares with an immediate without allocating a register.
RISC-V provides a single instruction to do compares, that being `lt`, and so you need to
use more than one for other variants, but in this case, i believe you need to allocate a register.

```

## Parents

- [63bbf665538d927bd56646e063821e31577f83f5](https://git.cafe/gitcafe/zig/commit/63bbf665538d927bd56646e063821e31577f83f5?format=markdown)

[Source at this commit](https://git.cafe/gitcafe/zig/tree/5e010b6deac7ad34f0cd06d507fc468fd98f9abc?format=markdown)