# start adding big endian RISC-V support · gitcafe/zig

[View on GitCafe](https://git.cafe/gitcafe/zig/commit/5d019abe4ec70373db7a75c2a8a3e2d76939817c)

Repository: [gitcafe/zig](https://git.cafe/gitcafe/zig)

Visibility: public

Requested revision: 5d019abe4ec70373db7a75c2a8a3e2d76939817c

Requested commit: 5d019abe4ec70373db7a75c2a8a3e2d76939817c

Commit: 5d019abe4ec70373db7a75c2a8a3e2d76939817c

Tree: 4ca5e04afceab7cc8e363d7adfe0436f54a3e82a

Author: Alex Rønne Petersen

Committer: Alex Rønne Petersen

## Message

```
start adding big endian RISC-V support

The big endian RISC-V effort is mostly driven by MIPS (the company) which is
pivoting to RISC-V, and presumably needs a big endian variant to fill the niche
that big endian MIPS (the ISA) did.

GCC already supports these targets, but LLVM support will only appear in 22;
this commit just adds the necessary target knowledge and checks on our end.

```

## Parents

- [12686d9b7df8fe4c2663cd8e2136991dc3cf661c](https://git.cafe/gitcafe/zig/commit/12686d9b7df8fe4c2663cd8e2136991dc3cf661c?format=markdown)

[Source at this commit](https://git.cafe/gitcafe/zig/tree/5d019abe4ec70373db7a75c2a8a3e2d76939817c?format=markdown)