# better default enabled features for riscv · gitcafe/zig

[View on GitCafe](https://git.cafe/gitcafe/zig/commit/53210b2304990e9b3b0f35f847e13d4ea4ae4ced)

Repository: [gitcafe/zig](https://git.cafe/gitcafe/zig)

Visibility: public

Requested revision: 53210b2304990e9b3b0f35f847e13d4ea4ae4ced

Requested commit: 53210b2304990e9b3b0f35f847e13d4ea4ae4ced

Commit: 53210b2304990e9b3b0f35f847e13d4ea4ae4ced

Tree: 271d7690eebee3cb87ee4bcc3b62d0719b235856

Author: Andrew Kelley

Committer: Andrew Kelley

## Message

```
better default enabled features for riscv

Until ability to specify target CPU features (#2883) is done, this
commit gives riscv target better default features.

This side-steps #3275 which is a deficiency in compiler-rt when features
do not include 32 bit integer division.

With this commit, RISC-V compiler-rt tests pass and Hello World works
both pure-zig and with musl libc.

```

## Parents

- [9983501ff2cccf828bb357dddefb21e36813046d](https://git.cafe/gitcafe/zig/commit/9983501ff2cccf828bb357dddefb21e36813046d?format=markdown)

[Source at this commit](https://git.cafe/gitcafe/zig/tree/53210b2304990e9b3b0f35f847e13d4ea4ae4ced?format=markdown)