# Fix PowerPC syscalls causing invalid code from CBE · gitcafe/zig

[View on GitCafe](https://git.cafe/gitcafe/zig/commit/427f0025dbea242b4cd760e7569eb625da5c0910)

Repository: [gitcafe/zig](https://git.cafe/gitcafe/zig)

Visibility: public

Requested revision: 427f0025dbea242b4cd760e7569eb625da5c0910

Requested commit: 427f0025dbea242b4cd760e7569eb625da5c0910

Commit: 427f0025dbea242b4cd760e7569eb625da5c0910

Tree: e04df9f69910cefa826cc8ce32b614061df313f5

Author: taylor.fish

Committer: Alex Rønne Petersen

## Message

```
Fix PowerPC syscalls causing invalid code from CBE

Fixes #25209.

On PowerPC, some registers are both inputs to syscalls and clobbered by
them. An example is r0, which initially contains the syscall number, but
may be overwritten during execution of the syscall.

musl and glibc use a `+` (read-write) constraint to indicate this, which
isn't supported in Zig. The current implementation of PowerPC syscalls
in the Zig standard library instead lists these registers as both inputs
and clobbers, but this results in the C backend generating code that is
invalid for at least some C compilers, like GCC, which doesn't support
the specifying the same register as both an input and a clobber.

This PR changes the PowerPC syscall functions to list such registers as
inputs and outputs rather than inputs and clobbers. Thanks to jacobly0
who pointed out that it's possible to have multiple outputs; I had
gotten the wrong idea from the documentation.

```

## Parents

- [1f0cf7c5514587471a219c418c15b49413d0fd14](https://git.cafe/gitcafe/zig/commit/1f0cf7c5514587471a219c418c15b49413d0fd14?format=markdown)

[Source at this commit](https://git.cafe/gitcafe/zig/tree/427f0025dbea242b4cd760e7569eb625da5c0910?format=markdown)