# riscv: totally rewrite how we do loads and stores · gitcafe/zig

[View on GitCafe](https://git.cafe/gitcafe/zig/commit/350ad90ceec37cb3f152b666377f7f619981a60e)

Repository: [gitcafe/zig](https://git.cafe/gitcafe/zig)

Visibility: public

Requested revision: 350ad90ceec37cb3f152b666377f7f619981a60e

Requested commit: 350ad90ceec37cb3f152b666377f7f619981a60e

Commit: 350ad90ceec37cb3f152b666377f7f619981a60e

Tree: bbff3fca1130fb2f13461c26e9f57c7796f47b0c

Author: David Rubin

Committer: David Rubin

## Message

```
riscv: totally rewrite how we do loads and stores

this commit is a little too large to document fully, however the main gist of it this

- finish the `genInlineMemcpy` implement
- rename `setValue` to `genCopy` as I agree with jacob that it's a better name
- add in `genVarDbgInfo` for a better gdb experience
- follow the x86_64's method for genCall, as the procedure is very similar for us
- add `airSliceLen` as it's trivial
- change up the `airAddWithOverflow implementation a bit
- make sure to not spill of the elem_ty is 0 size
- correctly follow the RISC-V calling convention and spill the used calle saved registers in the prologue
and restore them in the epilogue
- add `address`, `deref`, and `offset` helper functions for MCValue. I must say I love these,
they make the code very readable and super verbose :)
- fix a `register_manager.zig` issue where when using the last register in the set, the value would overflow at comptime.
was happening because we were adding to `max_id` before subtracting from it.

```

## Parents

- [cbf62bd6dc1f020df1177b3c6bcf11ed945ac83b](https://git.cafe/gitcafe/zig/commit/cbf62bd6dc1f020df1177b3c6bcf11ed945ac83b?format=markdown)

[Source at this commit](https://git.cafe/gitcafe/zig/tree/350ad90ceec37cb3f152b666377f7f619981a60e?format=markdown)