# stage2: implement while loops \(bool condition\) · gitcafe/zig

[View on GitCafe](https://git.cafe/gitcafe/zig/commit/28a9da8bfc1a791e0eaf8c643827da88ea70f7d1)

Repository: [gitcafe/zig](https://git.cafe/gitcafe/zig)

Visibility: public

Requested revision: 28a9da8bfc1a791e0eaf8c643827da88ea70f7d1

Requested commit: 28a9da8bfc1a791e0eaf8c643827da88ea70f7d1

Commit: 28a9da8bfc1a791e0eaf8c643827da88ea70f7d1

Tree: b15f8dfea2858c058d878d4917812d28202fe727

Author: Andrew Kelley

Committer: Andrew Kelley

## Message

```
stage2: implement while loops (bool condition)

 * introduce a dump() function on Module.Fn which helpfully prints to
   stderr the ZIR representation of a function (can be called before
   attempting to codegen it). This is a debugging tool.
 * implement x86 codegen for loops
 * liveness: fix analysis of conditional branches. The logic was buggy
   in a couple ways:
   - it never actually saved the results into the IR instruction (fixed now)
   - it incorrectly labeled operands as dying when their true death was
     after the conditional branch ended (fixed now)
 * zir rendering is enhanced to show liveness analysis results. this
   helps when debugging liveness analysis.
 * fix bug in zir rendering not numbering instructions correctly

closes #6021

```

## Parents

- [576581bd7b78825ce27d6a73fc42dd90eab8fbd1](https://git.cafe/gitcafe/zig/commit/576581bd7b78825ce27d6a73fc42dd90eab8fbd1?format=markdown)

[Source at this commit](https://git.cafe/gitcafe/zig/tree/28a9da8bfc1a791e0eaf8c643827da88ea70f7d1?format=markdown)