# stage2 ARM: make sub_sp_scratch MIR instruction use r4 · gitcafe/zig

[View on GitCafe](https://git.cafe/gitcafe/zig/commit/258b058eecb54e160ac60e72b0354f99f3202bdf)

Repository: [gitcafe/zig](https://git.cafe/gitcafe/zig)

Visibility: public

Requested revision: 258b058eecb54e160ac60e72b0354f99f3202bdf

Requested commit: 258b058eecb54e160ac60e72b0354f99f3202bdf

Commit: 258b058eecb54e160ac60e72b0354f99f3202bdf

Tree: aee5b0c2b12871e9047d0983c1926afe29d6ac5a

Author: joachimschmidt557

Committer: joachimschmidt557

## Message

```
stage2 ARM: make sub_sp_scratch MIR instruction use r4

r0 is used for argument passing, so this register is not available as
a scratch register upon function entry.

```

## Parents

- [4521456f66122c6348ef6980ae1eecdb94f4f110](https://git.cafe/gitcafe/zig/commit/4521456f66122c6348ef6980ae1eecdb94f4f110?format=markdown)

[Source at this commit](https://git.cafe/gitcafe/zig/tree/258b058eecb54e160ac60e72b0354f99f3202bdf?format=markdown)