# stage2 ARM: fix shl for ints with bits \< 32 · gitcafe/zig

[View on GitCafe](https://git.cafe/gitcafe/zig/commit/2412ac2c5ffe9ef02fdcfa2806b5f5862d4e42f3)

Repository: [gitcafe/zig](https://git.cafe/gitcafe/zig)

Visibility: public

Requested revision: 2412ac2c5ffe9ef02fdcfa2806b5f5862d4e42f3

Requested commit: 2412ac2c5ffe9ef02fdcfa2806b5f5862d4e42f3

Commit: 2412ac2c5ffe9ef02fdcfa2806b5f5862d4e42f3

Tree: 5a55cd33546120089f182904580f38982087b47a

Author: joachimschmidt557

Committer: joachimschmidt557

## Message

```
stage2 ARM: fix shl for ints with bits < 32

```

## Parents

- [0eebdfcad38e1348ca5fb8a26e722803664a3ebb](https://git.cafe/gitcafe/zig/commit/0eebdfcad38e1348ca5fb8a26e722803664a3ebb?format=markdown)

[Source at this commit](https://git.cafe/gitcafe/zig/tree/2412ac2c5ffe9ef02fdcfa2806b5f5862d4e42f3?format=markdown)