# stage2: change max int align from 8 to 16 for more ISAs · gitcafe/zig

[View on GitCafe](https://git.cafe/gitcafe/zig/commit/0bebb688fbc4c6ffb88a2b0aefcf536143bb5f2e)

Repository: [gitcafe/zig](https://git.cafe/gitcafe/zig)

Visibility: public

Requested revision: 0bebb688fbc4c6ffb88a2b0aefcf536143bb5f2e

Requested commit: 0bebb688fbc4c6ffb88a2b0aefcf536143bb5f2e

Commit: 0bebb688fbc4c6ffb88a2b0aefcf536143bb5f2e

Tree: 9d6b8e844ab56425202e44c1be70260a099f203b

Author: Andrew Kelley

Committer: Andrew Kelley

## Message

```
stage2: change max int align from 8 to 16 for more ISAs

These targets now have a similar disagreement with LLVM about the
alignment of 128-bit integers as x86_64:
 * riscv64
 * powerpc64
 * powerpc64le
 * mips64
 * mips64el
 * sparcv9

See #2987

```

## Parents

- [af7e945a7dc00a2a5055d9770b9ecda253d64a8e](https://git.cafe/gitcafe/zig/commit/af7e945a7dc00a2a5055d9770b9ecda253d64a8e?format=markdown)

[Source at this commit](https://git.cafe/gitcafe/zig/tree/0bebb688fbc4c6ffb88a2b0aefcf536143bb5f2e?format=markdown)