# riscv: zero registers when using register-wide operations · gitcafe/zig

[View on GitCafe](https://git.cafe/gitcafe/zig/commit/083b7b483e1ad83d62ed7029822a82fff14953c5)

Repository: [gitcafe/zig](https://git.cafe/gitcafe/zig)

Visibility: public

Requested revision: 083b7b483e1ad83d62ed7029822a82fff14953c5

Requested commit: 083b7b483e1ad83d62ed7029822a82fff14953c5

Commit: 083b7b483e1ad83d62ed7029822a82fff14953c5

Tree: 3b534a1d71fa3bc1c511788d162db28b5250b470

Author: David Rubin

Committer: David Rubin

## Message

```
riscv: zero registers when using register-wide operations

what was happening is that instructions like `lb` were only affecting the lower bytes of the register and leaving the top dirty. this would lead to situtations were `cmp_eq` for example was using `xor`, which was failing because of the left-over stuff in the top of the register.

with this commit, we now zero out or truncate depending on the context, to ensure instructions like xor will provide proper results.

```

## Parents

- [b67995689df424a0cab9186fcaf7b09bb04ffc1a](https://git.cafe/gitcafe/zig/commit/b67995689df424a0cab9186fcaf7b09bb04ffc1a?format=markdown)

[Source at this commit](https://git.cafe/gitcafe/zig/tree/083b7b483e1ad83d62ed7029822a82fff14953c5?format=markdown)