# stage2 ARM: optimize airSliceElemVal for elem_size 1 or 4 · gitcafe/zig

[View on GitCafe](https://git.cafe/gitcafe/zig/commit/04f379dd414184a42412f4497b0573d7612d6730)

Repository: [gitcafe/zig](https://git.cafe/gitcafe/zig)

Visibility: public

Requested revision: 04f379dd414184a42412f4497b0573d7612d6730

Requested commit: 04f379dd414184a42412f4497b0573d7612d6730

Commit: 04f379dd414184a42412f4497b0573d7612d6730

Tree: b0cdc7bf12be59a5f28915485aaf7304c742dc15

Author: joachimschmidt557

Committer: Jakub Konka

## Message

```
stage2 ARM: optimize airSliceElemVal for elem_size 1 or 4

In these cases, the AIR inst can be lowered to only one ldr
instruction.

Also fixes shifts in arm.bits.Offset

```

## Parents

- [71321b694195a87ab7394a25badf5295eb01875e](https://git.cafe/gitcafe/zig/commit/71321b694195a87ab7394a25badf5295eb01875e?format=markdown)

[Source at this commit](https://git.cafe/gitcafe/zig/tree/04f379dd414184a42412f4497b0573d7612d6730?format=markdown)