stage2 ARM: optimize airSliceElemVal for elem_size 1 or 4
In these cases, the AIR inst can be lowered to only one ldr
instruction.
Also fixes shifts in arm.bits.Offset
04f379dd41joachimschmidt557 committed on 2/4/2022, 8:07:10 PM· committed by Jakub Konkaparent71321b6